(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of making a vertical channel device using buried source techniques to reduce the area of the active region in the fabrication of integrated circuits.
(2) Description of the Prior Art
A priority in integrated circuit chip fabrication technology today is in reducing the chip size. Workers in the art have striven to reduce the width of the polysilicon from 2 .mu.m, 1 .mu.m, 0.8 .mu.m, 0.5 .mu.m, to 0.35 .mu.m, etc. Most of the effort at reducing chip size is directed toward reducing the polysilicon size. At some point in the near future, the polysilicon width shrinkage will have reached its maximum effectiveness. Source and drain regions are planned and drawn at the chip surface, which wastes valuable underlying layout areas. The large field oxide areas are used for isolation only. For example, in FIG. 1, there is shown a portion of a partially completed integrated circuit. Field oxide regions 11 have been formed in and on the surface of the semiconductor substrate 10. Source contacts 20 and drain contacts 22 are shown in a finger-type layout on the surface of the integrated circuit chip. In order to further shrink the chip layout, the source and drain regions must be addressed.
U.S. Pat. No. 5,164,325 to Cogan et al shows the formation of a vertical channel device using a buried source/drain structure.